The present invention generally relates to NVSARM cell and array operations with improvements in defect detectabilities, coupling ratio for using SBPI scheme for Program and Program-Inhibit operations, and flexibility of flash data handling.
Using a typical 16T1b NVSRAM cell as an example, the issues about defective or weak bits exits in the extremely high density NVSRAM array with power voltage down to 1.2V VDD are presented here. The 16T1b NVSRAM cell includes one LV CMOS SRAM cell, one HV paired 3T Flash strings and one Bridge circuit sandwiched by above two circuits. The Flash's program and erase operations are preferably done by using the mainstream low-current, highly scalable, FN-channel tunneling scheme like NAND flash technology today.
The three key regular operations of the NVSRAM cell are explained below.    1) FSwrite operation: It is defined as “a write operation performed from each Flash cell into each corresponding SRAM cell of each NVSRAM cell simultaneously and collectively upon power up cycle.    2) SFwrite operation: It is defined as “a write operation performed from each SRAM cell into each corresponding Flash cell of each NVSRAM cell simultaneously and collectively upon the power loss cycle.    3) SRAM operations: The SRAM operations include the regular Read and Write operations of each SRAM cell with each Flash cell electrically un-present.
After whole NVSRAM memory chip erase operation via a FN-channel erasing scheme, all flash cells within the NVSRAM memory will be in an identical threshold voltage level Vt0≦−2.0V. But after the repeated stress of the long program and erase cycles, the Vt0 value might get harder below −2.0V. The Vt0 value will be getting higher to near or above 0V. Those cells correspond to so-called marginally erased cells. It is desired to have an extra function for the NVSRAM array, without having an overhead to add any extra transistors, to be able to detect those marginally erased cells in fast speed. In particular, the quick Vt0-check in unit of flexible sizes of Bit, Page and Chip is desired so that the addresses of the marginal-Vt0 NVSRAM cells can be quickly reported at I/O pins.    5) Similarly, after whole NVSRAM memory program operation via a FN-channel programming scheme, all paired flash cells in NVSRAM memory will be programmed to a desired logic states of “0” and “1”. For either “0” or “1” logic states, the Vt of one bit of the paired flash cells, MC1 and MC2, would be programmed to a threshold voltage level Vt1≧2.0V. And the other bit of the paired flash cells would remain at Vt0. But after the repeated stress of the long program and erase cycles, the Vt1 value might get harder above 2.0V. These cells are so-called marginally programmed cells, which Vt1 value will be getting lower to near 1.0V. Therefore, it is again very desirable, for production screen control and process yield improvement, to have another extra function for performing a quick Vt1-check in unit of flexible sizes of Bit, Page and Chip without having an overhead to add any extra transistors. This extra function should be able to provide a report of the addresses of the marginal-Vt1 cells at I/O pins.
In another aspect of NVSRAM cells and arrays, traditionally in order to improve FN Channel-Program and Channel-Erase operations for NVSRAM cell, Flash cell's Poly1-wing width is increased in layout in WL-direction to increase coupling ratio from poly2-gate to Poly1 -floating gate. Basically, it induces more HV charges by flash gate (WL) in the flash floating channel so that the SBPI HV is sufficient high for correcting NVSRAM operation. But increasing the flash cell's WL program voltage only results in the enhancement of the Program operation rather than Program-Inhibit operation. Higher WL voltage also results in higher WL stress and lower P/E endurance cycles for the NVSRAM cell. An alternative approach is to increase the overlapping area of Poly1-Poly2 in field region of each flash cell layout by keeping the flash cell channel length and width the same but increasing the Poly1-wing length to extend to field region between two adjacent BLs. But practically, this is not suitable for today's high-density NAND and other flash cells because there is no Poly1-wing extending over the field region in extremely high-density Flash design wherein the Poly1 layer is usually made self-aligned to active layer for cell size reduction. Therefore, more practical and economical approach is desired for increasing flash cell coupling ratio for those NVSRAM cell and the like using the SBPI scheme for Program and Program-Inhibit operations.
In yet another aspect of the NVSRAM cells and arrays, one drawback is lack of flexibility in association with a basic “store” operation followed by a “recall” operation to properly handle required erase operation on Flash part of the NVSRAM cell. In particular, typical NVSRAM cell has one Flash part per each SRAM part. After a regular power-on period and when VDD becomes stable, and during a regular SRAM operation, would the NVSRAM memory need to perform an erase operation on the Flash part so that they can be immediately ready for next auto-store or the software-store or hard-store commands can come in any time soon? Additionally, after a regular power-down or a sudden power loss, the final critical data stored in the SRAM part have to be stored into the Flash part with a very short time (e.g., 8 ms as specified in the regular NVSRAM spec). If the Flash part of the NNVSRAM was not being erased before the power-down, then it is forced to perform the erase first and then program second. The erase needs to an on-chip negative charge HV pump circuit to supply a VNN voltage and the program needs another on-chip positive charge pump to supply a VPP voltage. All these operations take time and have to be operated under the dropping VDD voltage, thus it makes the “store” operation very risky and unreliable. Besides, more NVSRAM system applications have a need to keep the flash data before the power-down happens. In view of this drawback, new NVSRAM cell with more built-in flexibility in store/recall handling is desired.
In view of above drawbacks in conventional NVSRAM operation and demand for new NVSRAM's applications to fast detect marginally erased/programmed cells, to enhance Program/Program-Inhibit operations, and to keep Flash old data and new updated data, the present invention of the preferred NVSRAM cell and array is aimed at providing one or more practical solutions or economic options over the prior arts.